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Industrial Research And Consultancy Centre
Patent
Method and System for One Time Programmable Memory for Encryption and Reconfigurable Circuits
Problem Statement

Current embedded memory solutions require additional masks and process modifications to standard CMOS flows, making them incompatible and less efficient. The need for secure, reliable, and CMOS-compatible memory for various applications such as chip IDs, analog trimming, and code storage remains unmet. Existing methods, including gate oxide breakdown and other anti-fuse technologies, do not fully address these needs due to limitations in security, compatibility, and operational efficiency.

Abstract

The invention provides a one-time programmable (OTP) memory device that integrates seamlessly with standard CMOS processes. It employs a Metal-Insulator-Metal (MIM) structure to create a reliable and secure memory that can generate security keys through a deterministic or probabilistic breakdown procedure. This approach eliminates the need for additional masks and process modifications while ensuring high security and reliability.

Uniqueness of the Solution
  • MIM Structure: Utilizes a Metal-Insulator-Metal layer configuration for the memory device. 
  • Breakdown Procedure: Generates security keys based on the electrical breakdown of the MIM structure, which can operate in deterministic or probabilistic modes. 
  • CMOS Compatibility: Designed to integrate with standard CMOS processes without additional masks or modifications. 
  • Fabrication Process: Involves depositing multiple layers (electrodes, isolation layer, MIM layer) using standard techniques like RF reactive metal deposition, dielectric sputter process, and chemical vapor deposition.
  • High Security: Enhanced by the randomness in the MIM breakdown process. 
  • CMOS Compatibility: No need for additional masks or process modifications. 
  • Reliability: Robust against cloning and duplication attempts. 
  • Flexibility: Can operate in deterministic or probabilistic modes to generate keys
Prototype Details

The prototype includes a substrate layer with a first electrode, an isolation layer, and a MIM layer, followed by a second electrode. The device operates by inducing an electrical breakdown in the MIM layer to generate security keys. The breakdown voltage can be controlled based on the size of the device and the desired mode of operation.

Current Status of Technology

The OTP memory has been fabricated in back-end-of-line at SCL Fab in India with 180 nm CMOS Fab line. This indigenous OTPM is in stage of demonstration for security key generation for security devices like smart card.

Technology readiness level

8

Societal Impact

The invention provides a robust, secure method for data storage and authentication, enhancing the security of electronic transactions and sensitive data. It helps protect against data breaches and unauthorized access, thereby fostering trust in electronic systems and reducing the risk of identity theft and fraud.

Relevant Industries, Domains and Applications
  • Semiconductor Industry: For secure embedded memory solutions in chips. 
  • Consumer Electronics: In devices requiring secure memory for IDs and authentication. 
  • Automotive Industry: For secure, reliable storage in automotive electronics. 
  • Financial Services: In secure transaction systems and hardware security modules. 
  • Telecommunications: For secure storage in communication devices.
Applications or Domain
  • Secure Storage: For sensitive information in various devices. 
  • Authentication Systems: Generation of unique security keys for secure access. 
  • Chip Identification: Embedding unique IDs in semiconductor chips. 
  • Analog Trimming: In precision analog circuits. Yield Enhancement: In semiconductor manufacturing processes.

Geography of IP

Type of IP

Application Number

201621031483

Filing Date
Grant Number

492478

Grant Date
Assignee(s)
Indian Institute of Technology Bombay
**This IP is owned by IIT Bombay**