A capacitor-less dynamic random access memory (DRAM) comprises a n-type semiconductor, a plurality of intrinsic semiconductor layers stacked above said n-type semiconductor, said intrinsic semiconductor layers are walled between a pair of Shallow Trench Isolation (STI) layers over said n-type semiconductor, a gate region separated by a gate oxide layer from said intrinsic semiconductor layers and a source region and a drain region formed by wrapping two extreme side walls of said second intrinsic semiconductor layer with doped semiconductors.
Type of IP
Faculty
Department
The invention can lead to more reliable and cost-effective memory devices, enhancing the performance of consumer electronics, computing devices, and embedded systems. It supports advancements in semiconductor technology, contributing to the development of high-performance, low-power memory solutions.
- Planar bulk capacitor-less DRAM design.
- Si/SiGe/Si hetero-structure for hole confinement.
- Impact ionization-based hole-generation.
- Low variability in threshold voltage.
- RDF immunity through dopant profile engineering.
- High-k dielectric gate materials.
- Reduced threshold voltage variability.
- Improved performance and reliability.
- Cost-effective planar bulk design.
- Enhanced charge storage and retention.
- Immunity to random dopant fluctuations.
3
The experimental memory functionality has been successfully demonstrated. This invention is in its stage of programming scheme optimization and endurance characterization for DRAM application.
- Semiconductor manufacturing.
- Memory device fabrication.
- Electronics and computer hardware.
- Dynamic Random Access Memory (DRAM) in computers and electronic devices.
- High-density memory applications.
- Embedded DRAM in system-on-chip (SoC) designs.
- Non-volatile memory applications with charge trap flash integration.