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Industrial Research And Consultancy Centre
Patent
Bulk Planar Capacitor-Less Dynamic Random Access Memory (DRAM)
Problem Statement

Existing DRAM cell technologies, including vertical and planar capacitor-less designs, suffer from limitations such as high variability in threshold voltage and the requirement for expensive SOI wafers. There is a need for a planar bulk capacitor-less DRAM with low threshold voltage variability and immunity to random dopant fluctuations.

Abstract

A capacitor-less dynamic random access memory (DRAM) comprises a n-type semiconductor, a plurality of intrinsic semiconductor layers stacked above said n-type semiconductor, said intrinsic semiconductor layers are walled between a pair of Shallow Trench Isolation (STI) layers over said n-type semiconductor, a gate region separated by a gate oxide layer from said intrinsic semiconductor layers and a source region and a drain region formed by wrapping two extreme side walls of said second intrinsic semiconductor layer with doped semiconductors.

Uniqueness of the Solution
  • Planar bulk capacitor-less DRAM design. 
  • Si/SiGe/Si hetero-structure for hole confinement. 
  • Impact ionization-based hole-generation. 
  • Low variability in threshold voltage. 
  • RDF immunity through dopant profile engineering. 
  • High-k dielectric gate materials.
  • Reduced threshold voltage variability. 
  • Improved performance and reliability.
  • Cost-effective planar bulk design. 
  • Enhanced charge storage and retention.
  • Immunity to random dopant fluctuations.
Prototype Details

The prototype consists of a MOSFET structure with an n+ well, intrinsic Si/SiGe/Si layers, Shallow Trench Isolation (STI) layers, and a gate region with high-k dielectrics. The design demonstrates charge storage and retention in a planar bulk configuration, showing improved threshold voltage stability and performance.

Current Status of Technology

The experimental memory functionality has been successfully demonstrated. This invention is in its stage of programming scheme optimization and endurance characterization for DRAM application.

Technology readiness level

3

Societal Impact

The invention can lead to more reliable and cost-effective memory devices, enhancing the performance of consumer electronics, computing devices, and embedded systems. It supports advancements in semiconductor technology, contributing to the development of high-performance, low-power memory solutions.

Relevant Industries, Domains and Applications
  • Semiconductor manufacturing. 
  • Memory device fabrication. 
  • Electronics and computer hardware.
Applications or Domain
  • Dynamic Random Access Memory (DRAM) in computers and electronic devices. 
  • High-density memory applications. 
  • Embedded DRAM in system-on-chip (SoC) designs. 
  • Non-volatile memory applications with charge trap flash integration.

Geography of IP

Type of IP

Application Number

1976/MUM/2015

Filing Date
Grant Number

507960

Grant Date
Assignee(s)
Indian Institute of Technology Bombay
**This IP is owned by IIT Bombay**