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Industrial Research And Consultancy Centre
Patent
A Non-Inverting Buck Boost Converter
Problem Statement

Traditional non-inverting buck-boost converters face challenges with using a single controller for both buck and boost modes, which limits optimization and increases resource consumption in FPGAs. This leads to inefficiencies in power management and higher heat generation.

Fig. 1 Block diagram of controller implemented using run-time partial reconfiguration

Abstract

This invention presents a new method for controlling a non-inverting buck-boost converter using an FPGA with dynamic reconfiguration. Unlike traditional converters that use a single controller for both buck and boost modes, this approach uses separate controllers optimized for each mode. The FPGA adjusts in real-time: configuring only the necessary circuits for the current mode (buck, boost, or both). This not only improves efficiency but also reduces power consumption by up to 48%. The system ensures smooth transitions between modes, maintaining stable output voltage even during changes in input voltage or load. Overall, it represents a significant advancement in power electronics, offering better performance and energy savings.

Uniqueness of the Solution
  • Dynamic Reconfiguration: Enables FPGA to switch between buck, boost, and combination modes on-the-fly, optimizing resource allocation and enhancing flexibility in power management. 
  • Resource Efficiency: Reduces FPGA resource usage by up to 48%, minimizing hardware footprint and lowering costs associated with design and implementation. 
  • Seamless Mode Transitions: Facilitates smooth transitions between different operational modes, ensuring continuous and stable performance under varying load and input conditions. 
  • Enhanced Voltage Regulation: Improves output voltage stability and accuracy, crucial for applications requiring consistent power supply across dynamic operating environments. 
  • Power Consumption Optimization: Lowers overall power consumption of the system by efficiently utilizing FPGA resources based on current operational requirements, contributing to energy savings. 
  • Improved Thermal Management: Mitigates heat generation within the FPGA, enhancing reliability and lifespan of electronic components while maintaining optimal operating temperatures. 
  • Scalability and Versatility: Provides scalability for future enhancements and versatility to adapt to different application requirements without significant hardware modifications, ensuring long-term usability and adaptability.
Prototype Details

The technology was demonstrated in lab environment using Run-Time Partial Reconfiguration of Xilinx Spartan-6 FPGA along with other associated components of buck-boost circuit.

Current Status of Technology

Further development/prototype manufacturing is not carried out, however the Run-time partial reconfiguration of FPGA remains a relevant technology in various applications.

Technology readiness level

4

Societal Impact
  • Enhances energy efficiency, reducing overall power consumption. 
  • Improves reliability and lifespan of electronic devices. 
  • Supports sustainable technology development. 
  • Enables stable power supply in various environments. 
  • Facilitates cost-effective design solutions. 
  • Contributes to reducing electronic waste.
Relevant Industries, Domains and Applications

Semiconductor Industry, Renewable Energy, Automotive, Consumer Electronics, Telecommunications, Industrial Automation, Smart Grid, Portable Electronics

Applications or Domain

Power Electronics, Renewable Energy Systems, Automotive Electronics, Industrial Automation, Consumer Electronics, Telecommunications, Portable Devices, Smart Grids

Geography of IP

Type of IP

Application Number

515/MUM/2013

Filing Date
Grant Number

428237

Grant Date
Assignee(s)
Indian Institute of Technology Bombay
**This IP is owned by IIT Bombay**