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Industrial Research And Consultancy Centre
Patent
Process and Temperature Tracking Bias Circuits for Realization of PT-Invariant Quantities in Analog Circuits
Abstract

The invention proposes a novel biasing technique that adjusts automatically to compensate for process and temperature variations, thereby stabilizing resistance and current references on-chip. This approach aims to eliminate the need for external components and digital calibration, reducing power consumption and enhancing reliability in analog circuit designs.

Figure (1) Layout and die photo of the constant Gm circuit; (2) (a) Beta multiplier-based Gm -R bias circuit, (b) Proposed PT-invariant on-chip resistor

Problem Statement

Current analog circuits suffer from significant variability in on-chip resistors and current sources due to process and temperature fluctuations. Existing solutions require expensive external components or complex digital calibration methods, leading to increased power consumption and potential reliability issues. There is a critical need for a cost-effective and reliable solution that can stabilize on-chip resistors and current references without external dependencies, ensuring consistent performance across varying conditions in analog circuitry.

Uniqueness of the Solution
  • Constant On-chip Resistance: This technology utilizes process and temperature tracking bias circuits for maintaining constant on-chip resistance without external components. 
  • PT Invariance: It achieves PT-invariant quantities such as stable transconductance and PTAT current references across varying conditions. 
  • Reduced Cost: It eliminates the need for costly digital calibration methods and external precision resistors. 
  • Enhanced Reliability: It enhances analog circuit reliability by minimizing variability in resistors and current sources across different process corners and temperature ranges.
Prototype Details

This novel circuit is fabricated and tested on the silicon chip technology and evaluated for its basic concept, and its formulation is being confirmed to ensure realistic end-use application.

Current Status of Technology

The technology is currently being tested.

Technology readiness level

4

Societal Impact

This technology reduces electronic waste by promoting more reliable and durable analog circuits with longer operational lifespans. It lowers power consumption in electronic devices by eliminating the need for energy-intensive calibration techniques. It facilitates cost-effective production of electronic devices by reducing reliance on external components and calibration processes.

Applications or Domain
  • Signal Processing: Analog integrated circuits for signal processing and filtering applications
  • Sensors: Sensor interfaces require precise and stable current references
  • Electronics: Power management circuits in portable electronics for efficient energy utilization
  • Other Industries: Semiconductors, Telecommunication, Automotive Electronics

Geography of IP

Type of IP

Application Number

73/MUM/2012

Filing Date
Grant Number

410890

Grant Date
Assignee(s)
Indian Institute of Technology Bombay
**This IP is owned by IIT Bombay**