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Industrial Research And Consultancy Centre
Patent
Single Event Soft Error (SE) Tolerant Latch
Abstract

The invention disclosed is a latch designed to withstand single event soft errors (SE), particularly in digital circuits vulnerable to transient faults caused by cosmic rays or alpha particles. It features a flexible architecture comprising different configurations of p-channel and n-channel transistors (1P-2N or 2P-1N), coupled with auxiliary elements like back-to-back inverters or 3-input C-elements. A clocked circuit module ensures proper timing, enabling the latch to operate in transparent mode for writing data and in hold mode for storing data securely. This SE-tolerant design aims to mitigate soft errors in memory cells and sequential logic, enhancing reliability in scaled-down digital circuits prone to environmental disturbances.

Type of IP

Category of Patent

Societal Impact
  • Enhances reliability of medical devices and space exploration technology by reducing errors caused by environmental factors. 
  • Improves data accuracy in critical applications, ensuring safety and efficiency in digital systems used in healthcare and aerospace industries.
Salient technical features and Advantages of the Technology
  • Integrates multiple transistor configurations (1P-2N and 2P-1N) for adaptive resilience against soft errors. 
  • Utilizes auxiliary elements such as back-to-back inverters and 3-input C-elements for enhanced error detection. 
  • Includes clocked circuit modules to ensure precise timing for data storage and retrieval. 
  • Operates in both transparent and hold modes, facilitating seamless data writing and stable storage. 
  • Addresses single event soft errors in digital circuits, crucial for reliability in space and medical technology. 
  • Offers flexibility in configuration to optimize performance based on specific application requirements.


  • Integrates multiple transistor configurations (1P-2N and 2P-1N) for adaptive resilience against soft errors. 
  • Utilizes auxiliary elements such as back-to-back inverters and 3-input C-elements for enhanced error detection. 
  • Includes clocked circuit modules to ensure precise timing for data storage and retrieval. 
  • Operates in both transparent and hold modes, facilitating seamless data writing and stable storage. 
  • Addresses single event soft errors in digital circuits, crucial for reliability in space and medical technology. 
  • Offers flexibility in configuration to optimize performance based on specific application requirements.
Technology readiness level

3

Current Status of Technology

The complete circuit is simulated and the results are demonstrated using circuit    simulation.

Relevant Industries

Biomedical, aerospace and defense, space agency, semiconductors

Applications or Domain
  • Used in spacecraft electronics to ensure reliability and accuracy of data transmission. 
  • Applied in medical equipment to maintain consistent performance and data integrity during patient monitoring.