This novel circuit aims to provide precise measurements of time delays in digital circuits, particularly in memory chips, by using programmable delay elements. Below, is the description of the invention:
Time to Digital Converter (TDC):
- Converts time intervals into digital data.
- Uses two stages of delay elements to measure time intervals.
- First stage: Primary delay elements with a larger step size.
- Second stage: Secondary delay elements with a smaller step size.
- Both stages have multiple ring oscillators (loops of delay elements).
- Can operate in three modes: test, calibration, and functional.
- In test mode, the ring oscillators are separated to check functionality.
Integrated Circuit for Measuring SRAM Delay:
- Designed to measure delays within Static Random Access Memory (SRAM) on a chip.
- Combines the TDC with an SRAM block.
- TDC block has:
- Primary and secondary delay elements arranged in ring oscillators.
- A control unit for managing the TDC.
- A parallel-to-series converter for processing the output data.
- SRAM block includes an array of memory cells.
- Can operate in modes for both internal chip memory and external memory interaction
- Multi-Resolution TDC: The invention features a multi-resolution based time to digital converter (TDC) for precise on-chip delay measurement in SRAM.
- Programmable Delay Elements: Includes primary and secondary programmable linear delay elements arranged in multiple ring oscillator units for flexible step sizes.
- Operating Modes: The TDC operates in test, calibration, and functional modes, with separated ring oscillator units during the test mode.
- Adjustable Range and Resolution: The TDC's range and resolution are adjustable by varying the step sizes of the primary and secondary delay elements.
- Integrated Control and Conversion: Incorporates at least one TDC control unit and a parallel-series converter for enhanced control and output.
- SRAM Integration: The invention integrates the TDC with an SRAM block, enabling internal and external memory operations.
- Multi-Resolution TDC: The invention features a multi-resolution based time to digital converter (TDC) for precise on-chip delay measurement in SRAM.
- Programmable Delay Elements: Includes primary and secondary programmable linear delay elements arranged in multiple ring oscillator units for flexible step sizes.
- Operating Modes: The TDC operates in test, calibration, and functional modes, with separated ring oscillator units during the test mode.
- Adjustable Range and Resolution: The TDC's range and resolution are adjustable by varying the step sizes of the primary and secondary delay elements.
- Integrated Control and Conversion: Incorporates at least one TDC control unit and a parallel-series converter for enhanced control and output.
- SRAM Integration: The invention integrates the TDC with an SRAM block, enabling internal and external memory operations.
- Prototype Tested: Successfully demonstrated using circuit simulations the on-chip delay meaurement in SRAM.
- Operational Modes Validated: Effective in test, calibration, and functional modes.
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- Improved performance of Electronic Devices: Better memory and faster execution.
- Internet access: In rural areas, where the internet may be limited, technologies powered by this advancement can improve network speed and access to online resources.
- Safety and Infrastructure Development: In cities, applications in automotive and infrastructure sectors can lead to the development of safer transportation systems and more efficient urban infrastructure.
All those industries that require systems with precise timing and reliable memory operations can benefit from this invention like Semiconductor industry, Electronics, Telecommunication, Data Centers, Automotive industry, Aerospace and defense.
- Semiconductor Testing: Can be used in the testing and validation of integrated circuit performance, particularly in SRAM and other memory components.
- High-Speed Computing: Essential for timing analysis and delay measurement in high-speed processors and system-on-chip (SoC) designs to enhance performance and reliability.
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