When Integrated circuits are fabricated, a copper layer that forms the contacts is deposited on a low dielectric (the measure of electrical insulation) material layer coated on a semiconductor material substrate. In order to reduce RC time constant (the time to charge a capacitor) associated with the integrated circuits and to improve the frequency or speed of operation of integrated circuits traditional methods used result in a high dielectric constant.

Prof. R. O. Dusane and his students of Department of Metallurgical Engineering and Materials Science have formulated a method of depositing an amorphous SiC:H barrier layer on a low dielectric material layer. The method is simple and convenient to carry out, is cost effective and gives rise to a composite layer which lowers leakage of current. The layer is also of reduced thickness leading to lower costs of manufacture. The amorphous SiC:H is deposited to form the barrier layer on deposited material of low dielectric constant that is coated on the silicon layer. The barrier layer is deposited by exposing the material layer to hot wire chemical vapour deposition (HWCVD) using a mixture of silane and acetylene gases at a temperature of 200 to 300o C and pressure of 100 to 200 mTorr. HWCVD is done by heating a tungsten wire at 1700 to 1900o C.

The invention of depositing a barrier layer on the dielectric material layer by HWCVD eliminates the use of RF generators and impedance matching circuits thereby rendering the process simple and convenient to carry and also making it more cost effective. Further the process has been shown not to damage the dielectric layer. A barrier layer of 10 nanometers is adequate to prevent the copper diffusion into the dielectric material layer. The composite layer of barrier material and low dielectric constant material has reduced leakage of current. Thus Integrated circuits fabricated using the composite layer thus designed will have reduced RC time constant and improved frequency.