The present invention proposes a new capaciuvely coupled transmitter and a receiver with conventional sense amplifier based flip-flop and analog equalizer for high-speed low-power communication over long on-chip wires. The proposed signaling scheme has been designed in 90nm CMOS process. The proposed scheme can transmit and receive data at a rate of 3.45Gbps over a l Omm long wire consuming 0.1 07pJ/bit. Monte Carlo and process corner simulations show the proposed signaling scheme allows up to 30bps of data rate even in the presence of intra-die and inter-die process variations.