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Industrial Research And Consultancy Centre
Patent
Fermi-Level Depinning Structures for Semiconductor Devices
Abstract

A new method improves how metals connect with semiconductors by adding a very thin layer of black phosphorus in between. This layer helps electric current flow more easily or stop more effectively based on what the device needs. As a result, electronic parts like chips and sensors can work faster, use less power, and last longer. 

The design also solves a common problem in semiconductor technology by better controlling how energy levels line up at the connection point. The black phosphorus layer has special properties that can be adjusted by changing its thickness. It’s made at room temperature, without using any harmful chemicals, making the process safer, cheaper, and easier to scale.

Figure (1a) Device schematic for electrical characterization; (1b) Profilometer measurement of multilayer-BP flake. Inset: Microscopic image of exfoliated BP flakes at 50 µm scale; (1c) Raman Spectroscopy of exfoliated BP layer

Problem Statement

In many modern electronic devices, when metal connects with certain materials like Germanium (a type of semiconductor), the flow of electric current is blocked or slowed down due to a natural energy barrier. This issue, known as “Fermi-level pinning,” limits how efficiently these devices can perform, especially for high-speed or low-power electronics.

Uniqueness of the Solution
  • Black Phosphorus Depinning Layer: This product uses a multilayer black phosphorus film that stops unwanted energy trapping, so electrons move freely. 
  • Tunable Contact Behavior: This feature lets designers switch between easy flow (Ohmic) or controlled barrier (Schottky) by changing substrate type. 
  • Low Resistance Interface: This product avoids bulky interlayers; its thin film keeps resistance low and power losses minimal. 
  • Simple Mechanical Exfoliation: This feature relies on peeling thin layers with tape— no complex chemical steps needed. 
  • Wide Compatibility: This product works with standard metals (like tungsten) and common semiconductors (like Ge), making it easy to adopt.
Prototype Details

In the lab, researchers cleaned Germanium wafers, peeled on a ~100 nm black phosphorus film, then pressed a tungsten probe on top and a gold contact underneath. They measured electrical currents in a dark, enclosed station immediately after preparation. Microscopy, profilometry, and light-scattering tests confirmed film thickness and quality.

Current Status of Technology

The technology has been tested in a laboratory setting. Researchers built a working version of the device and successfully showed that it improves electrical performance using this new method. All tests were done on real materials using standard lab equipment, and the results were measured and confirmed.

Technology readiness level

5

Societal Impact

By slashing the wasteful resistance at tiny metal-semiconductor junctions, this innovation helps circuits switch faster while sipping far less power. In portable devices, that means noticeably longer run-times between charges—so smartphones, tablets, and wearables can last through a full day (or more) of heavy use. In large-scale computing centers, lower power draw reduces electricity bills and eases cooling demands, cutting both operational costs and carbon footprints. Cooler-running chips are also more reliable, shrinking the risk of heat-related failures. Altogether, the technology paves the way for slimmer, lighter electronics, extended-life batteries, and greener data processing—delivering clear benefits for end users, manufacturers, and the planet.

Relevant Industries, Domains and Applications
  • Semiconductor and chip manufacturing 
  • Electronics and computing hardware 
  • Sensor and communication device industries 
  • Advanced material engineering research

Geography of IP

Type of IP

Application Number

201921036221

Filing Date
Grant Number

538912

Grant Date
Assignee(s)
Indian Institute of Technology Bombay
**This IP is owned by IIT Bombay**