Accurate estimation of manufacturing variations can improve circuit performance New experimentally validated model accounts for manufacturing process variations while designing ultra-dense electronic circuits.
Silicon-based electronic circuits are continuously getting smaller. The Taiwanese manufacturer
TSMC currently makes chips with the smallest feature of the circuit measuring just 7
nanometers, with millions of such components packed on a single chip. The process of
manufacturing such ultra-dense circuits is complex. Despite world-class control, there are tiny
fluctuations in the nanoscale dimensions. Thus, each transistor is slightly different from another
across chips and even on the same chip. A circuit designer must account for such variations to
ensure that each of the billions of chips produced works as expected. Thus, a model to account
for such nanoscale variations in manufacturing is essential.
Dr Amita Rawat and Prof Udayan Ganguly from the Department of Electrical Engineering,
Indian Institute of Technology, Bombay (IIT Bombay), in collaboration with researchers from
IMEC, Leuven, Belgium, have experimentally validated their previously proposed method to
estimate the change in performance of an electronic circuit caused by manufacturing variations.
This is the first time that the experimental validation of variations predicted using physics-
based modelling has been reported. The predictions can be integrated with circuit design
softwares, thus making it possible to design better-performing circuits. This work was partially
funded by the Indian Institute of Technology Nano Fabrication Lab (IITBNF Lab), the Ministry
of Human Resource Development (MHRD), and the Department of Science and Technology
The building block of electronic circuits is MOSFET or Metal-Oxide-Semiconductor Field-
Effect Transistor. It is a three-terminal device with a semiconductor channel between its
terminals. Atomic impurities, called dopants, are added to the semiconductor to control its
current conducting capacity. The third terminal, called the gate, is made of metal or polysilicon
and insulated from the channel by an oxide layer. The gate voltage is used to control the current
in the channel.
Patterns are drawn using UV light on semiconductor chips to mark the channel, gate,
interconnects, and other circuit components. Patterns with lines and spaces smaller than 10
nanometer tend to have fluctuations of about a nanometer. It is also challenging to place dopant
atoms perfectly. The gate metal has nanoscale crystals that are not oriented uniformly in the
same direction leading to different atomic interfaces between metal crystal and gate insulator.
These local physical variations can significantly affect the electrical properties of the transistor.
“For example, the variation in how metal is deposited affects the value of the gate voltage at
which the transistor starts conducting current,” explains Dr Rawat, the lead author of the study.
As the building blocks of electronic circuits approach the atomic scale, the physical variations
become substantial compared to the component dimensions. In commercially-used design and
simulation softwares, circuit performance is inexactly evaluated based on simple variation in
electrical properties of the transistor that is increasingly inaccurate as transistors shrink. “We
provide process specific physics-based estimates of the electrical variation. It enables a more
accurate evaluation of the circuit performance,” says Dr Rawat. “The designers can also get an
idea of how the variation will alter if they change from one manufacturing process to another,”
To find the influence of the physical variations on the circuit performance, engineers first need
to evaluate its effect on the transistor’s electrical properties. Currently, computational methods
are used to study the structures of a few hundreds of transistors to find variations in electrical
properties. With hours of costly simulations needed to calculate each transistor’s parameters,
the process is computationally expensive and time-consuming. “Also, this method does not
provide a simple, intuitive model connecting the structural variations to electrical variations of
the transistors, necessary for the circuit designers,” comments Prof Ganguly.
“Our team developed the theoretical modelling of variability over nine years and three PhD
theses. The journey is chronicled in a magazine article in IEEE Nanotechnology Magazine.
Now our work has reached the experimental validation phase,” says Prof Ganguly.
The researchers created a mathematical model that accurately predicts variations in the
transistor electrical properties based on the changes in the physical parameters, such as
fluctuations of the pattern lines or metal nanocrystal orientation. The same model works for
any manufacturing process. They used this transistor variation data to create a ‘variability-
aware’ transistor model to be used in a commercial design and simulation software. Thus
circuits designed using this model captures the actual variability due to the manufacturing
process, and designers can get an accurate estimation of the circuit performance. “The beauty
of our platform is that the circuit performance prediction can be made available commercially,
without significantly adding to the cost,” comments Dr Rawat.
“In addition to making it easier to design better-performing circuits, the proposed method can
also provide feedback to the foundry team for improving their processes,” says Dr Rawat. The
process designer can determine which process dependent inputs give the desired physical
variability parameters. “It is like building a bridge between the circuit designers and the process
In the current study, the researchers used their model to predict the physical variations for the
14nm technology process. They compared these values with the experimentally measured
physical variations and found them to match well. They also estimated the variations in
electrical properties of the transistor, and these agreed with the experimentally measured
variations of a cluster of 250 transistors made with the 14nm technology. The worst and best
case errors were within acceptable limits. “Such elaborate experimental validation has not been
reported earlier,” remarks Dr Rawat.
The researchers plan to provide this framework as a technology package to be plugged into the
circuit design software. “We need to collaborate with foundries to access the latest data of
manufacturing processes they use. We can create the process-specific package and get it
validated from the foundry. It can evolve into an industry standard,” informs Dr Rawat.